SANTA CLARA, CA--(Marketwire - Sep 27, 2012) -
Chris Rowen, CTO and Founder, Tensilica
Dr. Rowen will present "The Protocol-Processing Dataplane: Extensible Muitiprocessors in Networking, Wireless Stacks and Storage" at the 6th Annual Linley Tech Processor Conference. He will discuss tough problems, such as accelerating Snort, HSPA upper-layer processing, TCP, and storage management to motivate specific advances in defining a programming model and instruction set and how these problems extend into multiprocessor support. He will conclude by highlighting a method to automate the cogeneration of multiprocessor hardware, multiprocessor system models, and multiprocessor runtime software optimized for minimum energy.
The Linley Tech Processor Conference is a two-day event delivering in-depth information from analysts and industry leaders on the newest processors for networking in the enterprise, carrier, and cloud-computing markets.
Dr. Rowen will speak during Session 5: Building Communications SoCs With Licensable Processor Cores, on Wednesday, October 10, from 3:15 - 4:50 p.m.
The Linley Tech Processor Conference runs from October 10 - 11, 2012.
DoubleTree Hotel, San Jose, Calif.
Attendance is free to qualified attendees who register by October 4 at www.linleygroup.com/processor-conference
About Chris Rowen
Chris Rowen was a pioneer in the development of the RISC architecture at Stanford in the early 1980s and helped start MIPS in 1984, where he served as Vice President for Microprocessor Development. In 1996 he became Vice President and General Manager of Synopsys' Design Re-Use Group. He left Synopsys to start Tensilica because he had an idea for a unique processor architecture that was designed, from the beginning, to be easily and automatically configurable and extensible. He is currently the CTO of Tensilica, working on the most challenging uses of the technology. He received a B.A. in physics from Harvard University and an M.S. and Ph.D. in electrical engineering from Stanford University.
Tensilica, Inc. is the leader in dataplane processor IP cores, with almost 200 licensees. Dataplane processors (DPUs) combine the best capabilities of DSPs and CPUs while delivering 10 to 100x the performance because they can be optimized using Tensilica's automated design tools to meet specific and demanding signal processing performance targets. Tensilica's DPUs power SOC designs at system OEMs and seven out of the top 10 semiconductor companies for designs in mobile wireless, telecom and network infrastructure, computing and storage, and home and auto entertainment. Tensilica offers standard cores and hardware/software solutions that can be used as is or easily customized by semiconductor companies and OEMs for added differentiation. For more information on Tensilica's patented, benchmark-proven DPUs visit www.tensilica.com.