Contact Information: Contacts: Semitool, Inc. Paul Siblerud Vice President Semitool 406.752.2107 Pfeiffer High Investor Relations, Inc. Geoff High 303.393.7044
EMC-3D Consortium Develops Process and Cost Model for Interconnect Thru-Silicon-Via or (iTSV(TM)) Structures
EMC-3D Members Announce Sub $190.00 CoO Is Achievable Today With Integrated 5micron by 30micron via-First Chip Stacking Technology
| Source: Semitool
SANTA CLARA, CA--(Marketwire - September 4, 2008) - The EMC3D consortium, which has been
working on an interconnect Thru-Silicon-Via, or iTSV™ process flow,
today announced that the cost of ownership for a 10,000-wafers-per-month
capacity line is now achievable at less than $190 per wafer.
Rozalia Beica, program manager of EMC3D and TSV director at
consortium-member Semitool, Inc. (NASDAQ : SMTL ) in the United States, said,
"The
via-first feature size of 5 microns in diameter by 30 microns deep was
chosen because of the challenges these dimensions present for etch and
deposition, as well as the increased interest and customer requests that
have been received through the consortium."
The integrated process includes litho and hard mask for the etch process,
DRIE for the via creation, thermal and CVD liner and barrier, wet copper
seed, copper electroplate fill, CMP and associated wafer cleans to complete
the via. The wafers are then processed using standard CMOS technology and
finally passed back to the TSV group for backside processing, including
thinning, lithography, copper redistribution, solder bump, dicing and
die-to-wafer-placement using temporary adhesive bonding before the final
die attach step for a complete process flow.
"The advances we have achieved in silicon etch, barrier and seed technology
have been quite impressive," said Hind Beaujon, business manager of Alcatel
in France. "In fact, the integration between the process steps is better
understood and allows companies to estimate overall costs much more
accurately."
Mark Scannell, microelectronics program manager of CEA-Leti in Grenoble,
France, said, "This technology utilizes an already established and accepted
set of equipment used in the advanced CMOS and wafer-level packaging
industries. The challenges are improving the integrated relationship of
process steps such as etch, deposition, copper fill and CMP, as well as
improving the speed and accuracy of the die-to-wafer placement during die
attach. Many of the unit processes are well understood and characterized.
The challenges now are to bring the technology to mass production in a cost
effective package."
Dr. Yoon-Chul Sohn of Samsung SAIT in Korea, said, "The next challenge is
to design an effective 3D structure for better electrical and thermal
performance and determine its relationship with material defects,
mechanical stress and electro-migration on these features."
"The EMC-3D cost model identifies the current complete Cost of Ownership to
be $189 for all the iTSV steps," said Markus Wimplinger, EV Group's
technology development and IP director. "This model allows us to identify
the cost improvement programs needed to bring the price below $145 per
wafer. The cost model clearly shows that reducing via size will enable
lower Cost of Ownership. Vias with reduced dimensions in turn require
thinner wafers that require unique, reliable handling solutions."
About EMC-3D (or EMC3D)
EMC3D (Semiconductor 3D Equipment and Materials Consortium) was created in
September 2006 to develop a new 3D market and technology by demonstrating a
cost-effective, manufacturable, stackable TSV interconnection process. TSV
processes will be developed for chip integration and MEMS/sensor packaging
that are based on plated metal electrodes and thinned wafers. For more
information, see www.EMC3D.org.
Contacts for EMC3D Members include:
Equipment Members:
Alcatel, France; (PARIS : CGEP ) and (NYSE : ALA ) Jean-Marc Gruffat, Director
of Business Development
Technology: Si and dielectric etching using DRIE
Datacon Technology GmbH, Austria; Christoph Scheiring, Director Product
Marketing
Technology: Precision Diebonding & Sorting
EV Group, Austria; Thorsten Matthias, Director of Technology North America
Technology: bonding, thin wafer handling, mask alignment lithography,
conformal coat and develop
SEMITOOL Inc, USA; (NASDAQ : SMTL ), Rozalia Beica, 3D Business unit director
Technology: electroplating, metal/barrier etch, photoresist strip, wafer
cleaning and thinning
XSiL Ltd, Ireland; Mr Joseph Callaghan, Via Team Leader
Technology: Si laser machining, via drilling, and wafer dicing
Isonics Corp, USA; (OTCBB : ISON ) Fred Schiele, V.P. and General Manager
Technology: wafer service (reclaim and test wafers, wafer thinning, and
thick-film SOI wafers)
Materials Members:
AZ Electronic Materials, USA; Aldo Orsi, Global Product Manager
Technology: positive and negative acting photoresists
Enthone (Cookson Electronics), USA; Yun Zhang, Director, R&D and Technical
Marketing
Technology: chemistry for electroplating and metal etch
Rohm and Haas, USA; Bob Forman, Advanced Packaging Business Manager
Technology: chemistry for lithography, plating, etching, dielectric
formation, and bonding
Brewer Science, Inc., USA; Laura Mauer, Associate Director of R&D Advanced
Technologies
Technology: Materials used in litho, wafer thinning, wafer etching and
anti-reflective coatings as well as spin-coat/develop/bake equipment.
Technology Members:
CEA-LETI, Grenoble France; Mark Scannell, Microelectronics Program Manager
Fraunhofer IZM, Germany; Jürgen Wolf, Group and Project Manager
NXP, Dr. Fred Roozeboom, Technical Advisor
KAIST (Korea Advanced Institute of Science and Technology), Korea; Dr.
Kyung-Wook Paik, Professor
SAIT (Samsung Advanced Institute of Technology), Korea; Dr. Yoon-Chul Sohn,
Researcher
TAMU (Texas A&M University), USA; Dr. Manuel Soriaga, Professor